SystemVerilog based Verification services

SystemVerilog is an IEEE 1800 industry standard first unified Hardware Design and Verification Language (HDVL). SystemVerilog is built on top of Verilog 2001. SystemVerilog improves the productivity, readability, and reusability of Verilog based code. SystemVerilog brings a higher level of abstraction to design and verification. It is widely embraced and supported by multiple vendors of EDA tools and verification IP's, as well as interoperability between different tools and vendors.

Based on usage SystemVerilog is broadly divided into five parts: SystemVerilog for Design, SystemVerilog for Testbench, SystemVerilog Assertions, SystemVerilog for Direct Programming Interface and SystemVerilog for Application Programming Interface. Verification standards like UVM, OVM and VMM have been developed using SystemVerilog’s capabilities as a verification language with object oriented features.

Kasura has experience in developing verification suites using SystemVerilog and its associated methodologies. Kasura has also been involved in EDA tool projects that are based on extending SystemVerilog’s capabilities into the co-simulation domains. Kasura is also a technical partner in Synopsys VMM Catalyst Program.

Kasura has worked on verification projects using EDA tools like Synopsys VCS and Cadence Incisive simulator environments. Kasura also has proposed solutions for using SystemVerilog and SystemC together in a common environment with the aid of SystemVerilog’s Direct Programming Interface (DPI) thereby, affirming its faith in the potential that these two languages can fulfil in the system level design and verification domains.

Case Studies