Kasura offers technical services in the ESL domains of hardware modelling and functional virtual prototyping of systems. Kasura has executed projects for clients engaged in providing SOC solutions for wireless, automotive, consumer electronics and defence fields.

Kasura operates both offshoring and onsite models of projects and has a dedicated team comprising of individuals with skillsets in SystemC and SystemVerilog. The team at Kasura has always been upto date with latest methodologies like TLM2.0 library of SystemC and OVM/UVM verification methodologies of SystemVerilog.

Kasura executes projects in the following two major domains

SystemC based Hardware Modeling, Prototyping and Verification Services

SystemC is a set of classes in C++ developed with the intention of designing and representing hardware at higher levels of abstraction than provided by classical HDLs. The higher levels of abstraction prove useful in developing software early for complex SoCs and help identify transaction complexities via architectural exploration. SystemC has been adopted throughout the semiconductor industry as an abstract modelling language and has been maintained as an IEEE standard since 2005.

SystemVerilog based Verification services

SystemVerilog is an IEEE 1800 industry standard first unified Hardware Design and Verification Language (HDVL). SystemVerilog is built on top of Verilog 2001. SystemVerilog improves the productivity, readability, and reusability of Verilog based code. SystemVerilog brings a higher level of abstraction to design and verification. It is widely embraced and supported by multiple vendors of EDA tools and verification IP's, as well as interoperability between different tools and vendors.